The present invention relates generally to PNPN thyristor structures and more specifically to a PNPN thyristor structure with improved recovery time. These devices may be silicon controlled rectifiers (SCR) or gate turn-off SCRs (GTO-SCR). A GTO-SCR is a PNPN thyristor designed to be turned-off, usually by removing current from the cathode gate.
The turn-off sequence of the GTO-SCR is often described by three periods of time; storage time, fall time and tail time. Storage time is the period from the beginning of turn-off until the anode current begins to drop. This assumes turn-off is GTO action using cathode gate. This time is dependent upon the amount of charge stored in the SCR and how fast it can be removed. The fall time is the period during which the anode current drops from 90% to 10% of its initial value. It begins when enough stored charge is removed to allow the middle junction to become reverse biased. Once the junction is reverse biased, the SCR impedance increases which results in the fall of the anode current. The tail current time is the period during which the remaining stored charge is removed. Often this time is extended because BJT action replaces stored charge almost as fast as it is removed, dependent of the BJT current gain.
The turn-off time can be decreased by limiting the amount of charged stored during "on" operation. The two most common techniques are lifetime reduction and anode and/or cathode shorts. The lifetime can be reduced by doping with metal such as gold or by making defects with irradiation by high energy particles. These allow electrons and holes to more readily recombine reducing the number of free carriers at any given time. Anode or cathode shorts also reduce the number of free carriers for a given terminal current by decreasing the injection efficiency of the anode or cathode. With an anode short for example, there would be a region in the anode gate diffusion that is ohmically or electrically connected to the anode terminal. This is the "short" or "shunt". Some of the electrons injected by the N+ cathode go through this shunt region directly to the anode contact instead of crossing the anode/anode gate junction. This reduced the forward bias on the anode/anode gate junction which in turn reduces the holes injected by the P+ anode.
Both of these techniques have some disadvantages. They are more effective at lower current densities than higher. The concentration density of active metal or defects is limited by material and processing considerations. At carrier concentrations above 1E17, Auger recombination is dominant so the peak concentrations at high current densities are the same as if there was no lifetime reduction. However, lifetime reduction will increase the turn-on gate drive requirements and increase the "off" state leakage current.
Likewise the anode/cathode shorts become less effective at higher current densities since the junction voltages increase logarithmically with the junction current. The current through the resistive shunt is proportional to the voltage across the junction. Therefore the ratio of shunt current to junction current falls as the total anode terminal current increases. This makes the device difficult to turn on since the gate drive has to supply the shunt current. At some high current, the percentage of shunt current is too small to make a difference.
Thus it is an object of the present invention to provide a thyristor structure having fast turn-off effective at high current densities.
Another object of the present invention is to provide a fast turn-off thyristor structure without increasing the turn-on gate drive requirements.
These and other objects are achieved by providing a first active shunt region in the cathode gate region connected electrically to the anode terminal for shunting carriers around the anode gate region in response to the thyristor switch being on and a second active shunt region in the anode gate region connected electrically to the cathode terminal for shunting carriers around the cathode gate region in response to the thyristor being on. These active shunts are off when the main thyristor is off so that they do not increase the turn-on gate current and do not degrade the off state leakage.
The active shunts pass more current as free carrier concentration increases. This tends to limit the peak carrier concentration. For any given anode/cathode terminal current, the free carrier concentration is reduced below the level that would be present if the active shunts were absent. This reduces the total stored charge which decreases the turn-off time. Unlike previous devices using resistive shunts or lifetime reduction, the improved thyristor becomes faster as the terminal currents increase. The ratio of active shunt area to anode or cathode area could be adjusted to control the peak concentration value or even cause the thyristor to be self-current limiting.
The shunts are active regions which are inactive until the thyristor is turned on and remain active until after the thyristor is turned off. The anode gate contact region is closer to the active anode gate portion of the anode gate region than an active shunt portion of the anode gate region. Similarly, the cathode gate contact is closer to the active cathode gate portion of the cathode gate region than to the active shunt portion of the cathode gate region. Using a two transistor model for the thyristor, a first PNP transistor has its base and collector connected respectively to the collector and base of a first NPN transistor. The first PNP's emitter is the anode, the first PNP's base is the anode gate, the first NPN's base is the cathode gate and the first NPN's emitter is the cathode. The first shunt is a second NPN having its collector, base and emitter connected respectively to the emitter, collector and base of the first PNP transistor. The second shunt is a second PNP transistor having its collector, base and emitter connected respectively to the emitter, collector and base of the first NPN transistor.
In one preferred embodiment, the first NPN and PNP transistors are vertical transistors and the second NPN and PNP transistors are lateral transistors. In this embodiment, the base of the first NPN is a common region with the emitter of the second PNP. The collector of the first NPN is a common region with the base of the second PNP. The base of the first PNP is a common region with the emitter of the second NPN. Finally, the collector of the first PNP is a common region with the base of the second NPN. The first PNP's collector region has a boundary with the first NPN's base region and the first NPN's collector region has a boundary with the first PNP's base region. Also, the base of the first NPN is a first common region with the base of the second NPN and the base of the first PNP is a second common region with the base of the PNP. Using this four transistor analogy, the anode gate's contact region is closer to the first PNP's active base portion of the second common region than to the second PNP's active base portion of the second common region. Also, the cathode gate contact region is closer to the first NPN's active base portion of the first common region than to the second NPN active base portion of the first common region.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.